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12710hkim 20091026-s00005 no.a1618-1/11 LC749402BG overview LC749402BG is a picture quality improvement ic that processes the output signals to the lcd panel for high picture quality display. this ic performs various picture quality adju stments to provide the ideal correction for the display panel. it can support up to wvga/svga panels. * features (1) digital input/output ? digital ycbcr/ypbpr 24bit (4:4:4) or 16bit (4:2:2) or 8bit(itu-r bt.656) signal input ? digital rgb 24bit signal input ? digital rgb 18bit/24bit signal output ? digital ycbcr16bit (4:2:2)/24bit (4:4:4) signal output (2) image quality correction ? y image quality correction: luminance adjustment, contour correction, cdex (color depth expander), dynamic- , black/white stretch ? c image quality correction: color exciter, flesh tone correction, hue, color gain ? rgb image quality correction: brightness, contrast, white balance, black balance, correction (3) panel interface ? built-in panel driver timing controller ? panel protection timing signal generation ? backlight control pwm (video adaptive low power consumption processing) * : the LC749402BG video input should satisfy the following conditions: 40mhz or less operating frequency, 896 dots or less horizontal size, 768 lines or less vertical size. ordering number : ena1618 cmos ic silicon gate lcd picture quality improvement ic specifications of any and all sanyo semiconductor co.,l td. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' sproductsor equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, av equipment, communication device, office equipment, industrial equ ipment etc.). the products mentioned herein shall not be intended for use for any "special application" (medica l equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, t ransportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of re liability and can directly threaten human lives in case of failure or malfunction of the product or may cause har m to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for app lications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. if there is n o consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC749402BG no.a1618-2/11 lsi specifications ? supply voltage core: 1.2v i/o: 1.8v/2.85v/3.3v ? maximum operating frequency: 40mhz ? package: fbga96 principal applications ? lcd display equipment cdex (color depth expander) original cdex specifications absolute maximum ratings at ta = 25 c, dv ss = 0v, av ss _osc = 0v parameter symbol conditions ratings unit maximum supply voltage (i/o) dv dd _io -0.3 to +3.96 v maximum supply voltage (core) dv dd _core av dd _osc -0.3 to +1.8 v digital input voltage v i -0.3 to dv dd _io+0.3 v digital output voltage v o -0.3 to dv dd _io+0.3 v operating temperature topr -40 to +85 c storage temperature tstg -55 to +125 c allowable operating ranges at ta = -40 to +85 c, dv ss = 0v, av ss _osc = 0v ratings parameter symbol conditions min typ max unit 2.6 2.85 3.6 v supply voltage (i/o) dv dd _io 1.7 1.8 1.9 v supply voltage (i/o) dv dd _core av dd _osc 1.0 1.2 1.3 v input voltage range v in 0 d v dd _io v
LC749402BG no.a1618-3/11 dc characteristics at ta = -40 to +85 c, dv ss = 0v, av ss _osc = 0v, dv dd _io = 1.7v to 1.9v or 2.6v to 3.6v, dv dd _core = 1.0v to 1.3v ratings parameter symbol conditions min typ max unit cmos level inputs 0.7dv dd _io v input high-level voltage v ih cmos level schmitt inputs 0.7dv dd _io v cmos level inputs 0.3dv dd _io v input low-level voltage v il cmos level schmitt inputs 0.3dv dd _io v v i =dv dd _io 10 a input high-level current i ih v i =dv dd _io, with pull-down resistance 100 a input low-level current i il v i =dv ss -10 a cmos voltage: 2.6v to 3.6v pin d: i oh =-2ma pin f: i oh =-2ma (when set to 2ma) i oh =-4ma (when set to 4ma) pin g: i oh =-4ma (when set to 4ma) i oh =-8ma (when set to 8ma) pin h: i oh =-4ma dv dd _io-0.4 v output high-level voltage v oh cmos voltage: 1.7v to 1.9v pin d: i oh =-1ma pin f: i oh =-1ma (when set to 2ma) i oh =-2ma (when set to 4ma) pin g: i oh =-2ma (when set to 4ma) i oh =-4ma (when set to 8ma) pin h: i oh =-2ma dv dd _io-0.45 v output low-level voltage v ol cmos 0.4 v output leak current i oz at output of high-impedance -10 10 a pull-down resistor r dn typical conditions: ta=25 c dv dd _io=2.85v dv dd _core=1.2v 98 k typical conditions: ta=25 c dv dd _io=2.85v dv dd _core=1.2v tck=10mhz 10 steps 18 ma dynamic supply current i ddop typical conditions: ta=25 c dv dd _io=2.85v dv dd _core=1.2v tck=40mhz 10 steps 57 ma static supply current *1 i ddst typical conditions: ta=25 c dv dd _io=2.85v dv dd _core=1.2v outputs open v i =dv ss or dv dd _io 20 a * 1: there is a input terminal which builds in pull down resist ance. please note that there is no guarantee about static consumption current depending on circuit composition.
LC749402BG no.a1618-4/11 package dimensions fbga96 unit:mm (typ) 3387 pin assignment sanyo : isb96(6.0x6.0) 12345678910 abcdefghjk 6.0 6.0 0.75 0.5 0.75 0.5 0.1 1.05 max 0.29 side view side view top view bottom view LC749402BG top view b c d e f g h j k 1 2 3 4 5 6 7 8 9 10 a
LC749402BG no.a1618-5/11 block diagram mpu LC749402BG osd mix timing controller dhsi dvsi ddei dcki xrst srxd_sda scs_i2sel i2c/sio stxd sck_scl xtali color space convert blcon pwm pwm siosel horizontal contour hue fti color exciter color gain w/bl stretch dynamic color space convert white/black balance brightness/contrast rgb pdwn test color depth expander dither osdbl into panel protection dvso lti cti bypass tcon oscillator delay dcrout[7:0] dhso ddeo dcko grst flm oe cpv strb sp dexr pol dygin[7:0] dcbin[7:0] dcrin[7:0] dcbout[7:0] dygout[7:0]
LC749402BG no.a1618-6/11 pin functions in/output format pin no. pin symbol i/o format connecting destination remarks a1 av dd _osc p - core voltage analog connect this pin to b2 without fail. a2 stxd o d cmos digital sio data a3 sck_scl i c cmos digital bus clock (common to sio and i 2 c) a4 dbout7 o f cmos digital b/cb/c video (msb) a5 dbout4 o f cmos digital b/cb/c video a6 dbout1 o f cmos digital b/cb/c video a7 dgout6 o f cmos digital g/y video a8 dgout4 o f cmos digital g/y video a9 dgout3 o f cmos digital g/y video a10 dv dd _io p - io voltage digital connect this pin to b9 without fail b1 rc_bias i j resistor analog bias resistor connection (connect this pin to gnd with a 20k ) b2 av dd _osc p - core voltage analog b3 srxd_sda i/o h cmos digital sio data input/i 2 c data i/o b4 pwm o d cmos digital pulse width modulation waveform b5 dbout5 o f cmos digital b/cb/c video b6 dbout2 o f cmos digital b/cb/c video (6-bit output mode, lsb) b7 dgout7 o f cmos digital g/y video (msb) b8 dgout5 o f cmos digital g/y video b9 dv dd _io p - io voltage digital b10 dgout2 o f cmos digital g/y video (6-bit output mode, lsb) c1 dcrin0 i c cmos digital r/cr video. connect this pin to gnd when not to be used. c2 dcrin1 i c cmos digital r/cr video. connect this pin to gnd when not to be used. c3 av ss _osc p - gnd analog c4 into o d cmos digital interrupt c5 dbout6 o f cmos digital b/cb/c video c6 dbout3 o f cmos digital b/cb/c video c7 dbout0 o f cmos digital b/cb/c video (8-bit output mode, lsb) c8 dv dd _io p - io voltage digital c9 dgout1 o f cmos digital g/y video c10 dgout0 o f cmos digital g/y video (8-bit output mode, lsb) d1 dcrin2 i c cmos digital r/cr video. connect this pin to gnd when not to be used. d2 dcrin3 i c cmos digital r/cr video. connect this pin to gnd when not to be used. d3 dcrin4 i c cmos digital r/cr video. connect this pin to gnd when not to be used. d4 test i b cmos digital test (normally, connect this pin to gnd) d5 xrst i a cmos digital system reset (?l? reset) d6 dv dd _io p - io voltage digital d7 dv dd _io p - io voltage digital d8 drout7 o f cmos digital r/cr video (msb) d9 drout6 o f cmos digital r/cr video d10 drout5 o f cmos digital r/cr video continued on next page.
LC749402BG no.a1618-7/11 continued from preceding page. in/output format pin no. pin symbol i/o format connecting destination remarks e1 dcrin5 i c cmos digital r/cr video. connect this pin to gnd when not to be used. e2 dcrin6 i c cmos digital r/cr video. connect this pin to gnd when not to be used. e3 dcrin7 i c cmos digital r/cr video (msb). connect this pin to gnd when not to be used. e4 dv ss p - gnd digital e7 pdwn i a cmos digital ?h? power down. connect this pin to gnd when not to be used. e8 drout4 o f cmos digital r/cr video e9 drout3 o f cmos digital r/cr video e10 drout2 o f cmos digital r/cr video (6-bit output mode, lsb) f1 dygin0 i c cmos digital g/y/656 video (lsb). connect this pin to gnd when not to be used. f2 dygin1 i c cmos digital g/y/656 video. connect this pin to gnd when not to be used. f3 dygin2 i c cmos digital g/y/656 video. connect this pin to gnd when not to be used. f4 dv ss p - gnd digital f7 dv dd _core p - core voltage digital f8 drout1 o f cmos digital r/cr video f9 drout0 o f cmos digital r/cr video (8-bit output mode, lsb) f10 dcko o g cmos digital video clock g1 dygin3 i c cmos digital g/y/656 video. connect this pin to gnd when not to be used. g2 dygin4 i c cmos digital g/y/656 video. connect this pin to gnd when not to be used. g3 dygin5 i c cmos digital g/y/656 video. connect this pin to gnd when not to be used. g4 dv ss p - gnd digital g5 scs_i2sel i a cmos digital sio chip enable/i 2 c slave address switching g6 siosel i c cmos digital ?l?: i 2 c slave, ?h?: 4-wire sio g7 dv dd _core p - core voltage digital g8 dhso/sp2 o f cmos digital horizontal synchronizing signal/start pulse signal for source driver g9 dvso/flm2 o f cmos digital vertical synchronizing signal/start pulse signal for gate driver g10 ddeo o f cmos digital data enable signal h1 dygin6 i c cmos digital g/y/656 video. connect this pin to gnd when not to be used. h2 dygin7 i c cmos digital g/y/656 video (msb). connect this pin to gnd when not to be used. h3 dv ss p - gnd h4 dcbin6 i c cmos digital b/cb/c video. connect this pin to gnd when not to be used. h5 dvsi i c cmos digital vertical synchronizing signal h6 osdbl i c cmos digital data enable signal for external osd. connect this pin to gnd when not to be used. h7 flm o f cmos digital start pulse signal for gate driver h8 dv dd _core p - core voltage digital h9 dexr o f cmos digital reversed video signal output for dtr. low output when the dtr is off. h10 pol o f cmos digital voltage polarity selection signal for source driver continued on next page.
LC749402BG no.a1618-8/11 continued from preceding page. in/output format pin no. pin symbol i/o format connecting destination remarks j1 dcbin0 i c cmos digital b/cb/c video (lsb). connect to gnd when not to be used. j2 dv ss p - gnd digital j3 dcbin3 i c cmos digital b/cb/c video. connect this pin to gnd when not to be used. j4 dcbin5 i c cmos digital b/cb/c video. connect this pin to gnd when not to be used. j5 ddei i c cmos digital data enable signal, connect this pin to gnd in the internal generation mode j6 dhsi i c cmos digital horizontal synchronizing signal j7 grst o f cmos digital reset signal for gate driver j8 cpv o f cmos digital clock signal for gate driver j9 dv dd _core p - core voltage digital j10 sp o f cmos digital start pulse signal for source driver k1 dv ss p - gnd analog connect this pin to j2 without fail k2 dcbin1 i c cmos digital b/cb/c video. connect this pin to gnd when not to be used. k3 dcbin2 i c cmos digital b/cb/c video. connect this pin to gnd when not to be used. k4 dcbin4 i c cmos digital b/cb/c video. connect this pin to gnd when not to be used. k5 dcbin7 i c cmos digital b/cb/c video (msb). connect this pin to gnd when not to be used. k6 dcki i c cmos digital video clock k7 xtal1 i c cmos digital panel protection, pwm generation clock. connect this pin to gnd when not to be used. k8 oe o f cmos digital output enable signal for gate driver k9 strb o f cmos digital data strobe signal for source driver k10 dv dd _core p - core voltage digital connect this pin to j9 without fail
LC749402BG no.a1618-9/11 pin type in/output form function equival ent circuit application terminal a schmitt trigger cmos input xrst, pdwn, scs_i2sel b cmos input with built-in pull-down resistor test c cmos input sck_scl, siosel, dvsi, dhsi, ddei, osdbl, dygin7, dygin6, dygin5, dygin4, dygin3, dygin2, dygin1, dygin0, dcbin7, dcbin6, dcbin5, dcbin4, dcbin3, dcbin2, dcbin1, dcbin0, dcrin7, dcrin6, dcrin5, dcrin4, dcrin3, dcrin2, dcrin1, dcrin0 d 2ma 3-state drive cmos output stxd, pwm, into f 2ma/4ma switching 3-state drive cmos output dbout7, dbout6, dbout5, dbout4, dbout3, dbout2, dbout1, dbout0, drout7, drout6, drout5, drout4, drout3, drout2, drout1, drout0 dgout7, dgout6, dgout5, dgout4, dgout3, dgout2, dgout1, dgout0, dhso/sp2, dvso/flm2, ddeo flm, dexr, pol, grst, cpv, sp, oe, strb g 4ma/8ma switching 3-state drive cmos output dcko h 4ma 3-state drive cmos input/output srxd_sda j analog input/output rc_bias
LC749402BG no.a1618-10/11 i/o timing (1) input data timing pin name parameter symbol min typ max unit clock cycle t ck 25 ns dcki duty 50 % input data setup time (dv dd _io=2.6 to 3.6v) t su 3 ns input data setup time (dv dd _io=1.7 to 1.9v) t su 3 ns input data hold time (dv dd _io=2.6 to 3.6v) t hd 2 ns dcrin*, dygin*, dcbin*, dvsi, dhsi, ddei, osdbl input data hold time (dv dd _io=1.7 to 1.9v) t hd 2 ns * : the recommended duty cycle of input clock is 50% (2) output data timing pin name parameter symbol min typ max unit clock cycle t ck 25 ns dcko duty 50 % output data delay time (dv dd _io=2.6 to 3.6v) pin f: when set to 4ma pin g: when set to 8ma t ac -3 3 ns output data delay time (dv dd _io=2.6 to 3.6v) pin f: when set to 2ma pin g: when set to 4ma t ac -3 6 ns output data delay time (dv dd _io=1.7 to 1.9v) pin f: when set to 4ma pin g: when set to 8ma t ac -5 4 ns drout*, dgout*, dbout*, dvso, dhso, ddeo, dexr, pol, sp, strb, cpv, oe, flm, grst output data delay time (dv dd _io=1.7 to 1.9v) pin f: when set to 2ma pin g: when set to 4ma t ac -6 9 ns * when dcko is set to the forward rotation output. output load capacity: 5pf dv dd _io/2 t hi t li t ck t su t hd dcki dv dd _io/2 input data t lo t ck t ac dcko output data dv dd _io/2 dv dd _io/2 t ho
LC749402BG no.a1618-11/11 ps this catalog provides information as of january, 2010. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated v alues (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-qua lity high-reliability products, however, any and all semiconductor products fail or malfunction with some probabi lity. it is possible that these probabilistic failures or malfunction could give rise to accidents or events that co uld endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or e vents cannot occur. such measures include but are not limited to protective circuits and error prevention cir cuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other r ights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. information (including circuit diagrams and circuit par ameters) herein is for example only; it is not guaranteed for volume production. any and all information described or contained he rein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export contro l laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any i nformation storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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